This invention relates generally to semiconductor field effect transistors, and more particularly to field effect transistors having self-aligned source contacts.
The metal oxide semiconductor field effect transistor (MOSFET) is a device used to amplify or switch electronic signals. Power MOSFETs are well known for their ability to carry large currents in the on-state while withstanding large breakdown voltages in the off-state. In such devices, current flow between source and drain regions in a semiconductor substrate is controlled by a voltage applied to a gate electrode that is separated from the semiconductor surface by an insulator, typically silicon dioxide. In an n-type enhancement MOSFET, for example, a positive bias on the gate causes a surface inversion layer—or channel—to form in a p-type region under the gate oxide and thereby creates a conductive path between source and drain. The application of a positive drain voltage then produces current flow between drain and source. Lateral and vertical power MOSFET structures in silicon have been explored over the years, the former type having the drain, gate and source terminals on the same surface of the silicon wafer, the latter type having the source and drain on opposite surfaces of the wafer. Several different types of vertical power MOSFETs have been proposed, including the double-diffused MOSFET (DMOSFET) and the trench-gate or UMOSFET. These and other power MOSFETs are described in a textbook by B. Jayant Baliga entitled Power Semiconductor Devices, PWS Publishing Co. (1996), the disclosure of, which is hereby incorporated herein by reference.
Although silicon has been the material of choice for many semiconductor applications, its fundamental electronic structure and characteristics prevent its utilization beyond certain parameters. Thus, interest in power MOSFET devices has turned from silicon to other materials, including silicon carbide. SiC power switching devices have significant advantages over silicon devices, including faster switching speed, lower specific on-resistance and thus lower power losses. SiC has a breakdown electric field that is an order of magnitude higher than that of silicon, which allows for a thinner drift region and thus a lower drift region resistance.
In power DMOSFETs, an important performance parameter is the specific on-resistance (RON,SP), which is defined as the product of the resistance when the device is in the “on”, or highly conducting, state (low VDS), times the area of the device (units are Ω-cm2 or mΩ-cm2). Thus it is important to minimize both the resistance and the area of the device. For DMOSFETs in the blocking voltage regime of below about 600-1800V, a significant component of the total resistance is the resistance of the source contacts. Larger-area source contacts obviously have lower resistance, but increasing the contact area increases the total area of the device, and hence RON,SP. It is important to find ways to reduce the source contact resistance without increasing the area of the device.
In a conventional DMOSFET, the source contact is defined by photolithography, and the source contact must be separated from the edge of the gate by sufficient distance so that the source contact and gate cannot touch even under worst-case misalignment of the source contact mask. In addition, the actual functional area of the source contact is determined by the overlap of the source contact metal and the N+ implant that forms the source region in the semiconductor. Since the N+ implant is defined by a separate mask, relative misalignment of the source contact mask and the N+ implant mask can reduce the functional area of the source contact, thereby increasing source resistance and degrading performance.
It is desired to produce DMOSFETs and related devices wherein misalignments of source contact and gate are reduced or eliminated.